Metal-insulator-semiconductor (MIS), and more specifically metal-oxide-semiconductor (MOS) capacitor memory cells are forms of dynamic memory cells. In an MIS capacitor dynamic memory cell, the information is stored in the form of the presence vs absence of charge in a capacitor, thereby representing a binary digital state or bit of information. By "dynamic" is meant that the information in either one or the other (or both) of the two possible states tends to become degraded and to disappear with the passage of time.
An MOS capacitor memory cell in P-MOS technology can take the form of, for example, a portion of the surface of an N-type semiconductor body ("substrate") covered with a silicon dioxide insulator layer upon which is located a metal or metal-like electrical conducting plate. This conducting plate of the resulting MOS storage capacitor structure is maintained at a fixed negative reference voltage while electrical writing and reading pulses are applied to the semiconductor substrate surface portion of the capacitor underlying the plate. A positive-going voltage (or current) write-in pulse, applied to the semiconductor surface portion of the MOS storage capacitor, injects positive charges ("hole" minority carriers) into this semiconductor substrate surface portion, thereby bringing the MOS capacitor (P-MOS technology) into its binary digital "1" memory state ("full" of positive charge). On the other hand, a negative-going voltage (or current) write-in pulse applied to the semiconductor surface portion removes these positive charges from the semiconductor substrate surface portion, thereby sharply reducing the amount of positive charge in the semiconductor surface portion and bringing the MOS capacitor (P-MOS technology) into its binary digital "0" memory state ("empty" of positive charge). However, this binary 0 state tends to become degraded with the passage of time subsequent to the negative-going write-in pulse, because of the thermal regeneration of spurious minority carriers (positively charged holes) in the N-type semiconductor substrate. This degradation takes place within a time of the order of the semiconductor's thermal regeneration time, typically of the order of a few milliseconds or less. However, even in the face of this degradation of the "0" state, a negative-going write-in voltage pulse can remove the positive charges from the MOS substrate surface portion and thereby can produce the binary 0 state of information for storage in the MOS capacitor at least for a short period of time; whereas, the presence of positive charges in the substrate surface portion due to a positive-going write-in pulse to the substrate can produce the more stable binary 1 for storage in the MOS capacitor.
In U.S. Pat. No. 4,030,083 issued to me on June 14, 1977, refresh networks were disclosed for maintaining the binary digital (1 or 0) state of an MOS (metal oxide semiconductor) storage capacitor memory cell. Such refresh networks enabled refresh of the memory without the need for interrupting the electrical access capability for reading or writing. The refresh networks basically involved the use of an auxiliary A.C. pump source connected through the refresh network to the storage capacitor; thereby the A.C. source removed the spurious charges which were being generated in the empty (digital 0) state of the capacitor. Although the specific networks disclosed in my aforementioned patent are implementable in present day MOS technology, it may sometimes be desirable to modify such networks.